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APPLICATION NOTES AVAILABLE
AN99 * AN115 * AN120 * AN124 * AN133 * AN134 * AN135
Low Noise/Low Power/SPI Bus
X9421
Single Digitally Controlled (XDCP) Potentiometer
FEATURES * Single Voltage Potentiometer * 64 Resistor Taps * SPI Serial Interface for write, read, and transfer operations of the potentiometer * Wiper Resistance, 150 Typical at 5V * 4 Non-Volatile Data Registers * Non-Volatile Storage of Multiple Wiper Positions * Power On Recall. Loads Saved Wiper Position on Power Up. * Standby Current < 5A Max * VCC : 2.7V to 5.5V Operation * 2.5K, 10K End to End Resistance * 100 yr. Data Retention * Endurance: 100, 000 Data Changes per Bit per Register * 14-Lead TSSOP, 16-Lead SOIC * Low Power CMOS DESCRIPTION The X9421 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC RH/VH
address data status SPI bus interface
write read transfer inc / dec
Bus Interface & Control
Power On Recall Wiper Counter Register (WCR)
wiper POT
10K 64-taps
control
Data Registers 4 Bytes
VSS
RW/VW
RL/VL
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X9421
DETAILED FUNCTIONAL DIAGRAM
VCC
Power On Recall
DR0 DR1
10K 64--taps
HOLD
Control
CS
SCK SO SI
INTERFACE AND CONTROL CIRCUITRY
DR2 DR3
WIPER COUNTER REGISTER (WCR)
RH/VH
RL/VL RW/VW
A0
WP
DATA
VSS
CIRCUIT LEVEL APPLICATIONS * Vary the gain of a voltage amplifier * Provide programmable dc reference voltages for comparators and detectors * Control the volume in audio circuits * Trim out the offset voltage error in a voltage amplifier circuit * Set the output voltage of a voltage regulator * Trim the resistance in Wheatstone bridge circuits * Control the gain, characteristic frequency and Q-factor in filter circuits * Set the scale factor and zero point in sensor signal conditioning circuits * Vary the frequency and duty cycle of timer ICs * Vary the dc biasing of a pin diode attenuator in RF circuits * Provide a control variable (I, V, or R) in feedback circuits
SYSTEM LEVEL APPLICATIONS * Adjust the contrast in LCD displays * Control the power level of LED transmitters in communication systems * Set and regulate the DC biasing point in an RF power amplifier in wireless systems * Control the gain in audio and home entertainment systems * Provide the variable DC bias for tuners in RF wireless systems * Set the operating points in temperature control systems * Control the operating point for sensors in industrial systems * Trim offset and gain errors in artificial intelligent systems
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PIN CONFIGURATION
TSSOP S0 NC NC CS SCK SI VSS 1 2 3 4 5 6 7 X9421 14 13 12 11 10 9 8 VCC RL/VL RH/VH RW/VW HOLD A0 WP NC SO NC CS SCK SI NC VSS 1 2 3 4 5 6 7 8 X9421 SOIC 16 15 14 13 12 11 10 9 VCC NC RL/VL RH/VH RW/VW HOLD A0 WP
PIN ASSIGNMENTS TSSOP pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 4 5 6 8 9 10 11 12 13 14 16 1 7 15
SOIC pin
2 3
Symbol
SO NC NC CS SCK SI VSS WP A0 HOLD RW / VW RH / VH RL / VL VCC NC NC NC Serial Data Output No Connect No Connect Chip Select Serial Clock Serial Data Input System Ground
Brief Description
Hardware Write Protect Device Address Device select. Pause the serial bus. Wiper Terminal of the Potentiometer. High Terminal of the Potentiometer. Low Terminal of the Potentiometer. System Supply Voltage No Connect No Connect No Connect
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PIN DESCRIPTIONS Host Interface Pins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the potentiometer and pot register are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9421. Chip Select (CS) When CS is HIGH, the X9421 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9421, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A0) The address input is used to set the least significant bit of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9421. A maximum of 2 devices may occupy the SPI serial bus. Potentiometer Pins VH/RH, VL/RL The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW The wiper output is equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Writing to the Wiper Counter Register is not restricted. System/Digital Supply (VCC) VCC is the supply voltage for the system/digital section. VSS is the system ground. PRINCIPLES OF OPERATION The X9421 is a highly integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the XDCP potentiometer. Serial Interface The X9421 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9421 is comprised of one resistor array containing 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs).
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At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within the individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The block diagram of the potentiometer is shown in Figure 1. Wiper Counter Register (WCR) The X9421 contains a Wiper Counter Register. The WCR can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its data register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9421 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers The potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Register Descriptions Table 1. Data Registers, (6-bit), Nonvolatile 0
(MSB)
0
D5
D4
D3
D2
D1
D0
(LSB)
There are four 6-bit Data Registers associated with the potentiometer. - {D5~D0}: These bits are for general purpose Nonvolatile data storage or for storage of up to four different wiper values. Table 2. Wiper Counter Register, (6-bit), Volatile 0
(MSB)
0
WP5 WP4 WP3 WP2 WP1 WP0
(LSB)
- {WP5~WP0}: These bits specify the wiper position of the potentiometer.
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Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path From Interface Circuitry Register 0 8 Register 1 6
Serial Bus Input C O U N T E R D E C O D E
VH
Parallel Bus Input Wiper Counter Register (WCR)
REGISTER 2
REGISTER 3
IF WCR = 00[H] THEN VW = VL IF WCR = 3F[H] THEN VW = VH
INC/DEC Logic UP/DN Modified SCK UP/DN CLK VL
VW
Write in Process The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. INSTRUCTIONS Address/Identification (ID) Byte The first byte sent to the X9421 from the host, following a CS going HIGH to LOW, is called the Address or Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9421 this is fixed as 0101[B] (refer to Figure 2). The least significant bit in the ID byte selects one of two devices on the bus. The physical device address is defined by the state of the A0 input pin. The X9421 compares the serial data stream with the address input state; a successful compare of the address bit is required for the X9421 to successfully continue the command sequence. The A0 input can be actively driven by a CMOS input signal or tied to VCC or VSS. The remaining three bits in the ID byte must be set to 110.
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Figure 2. Address/Identification Byte Format
Device Type Identifier
0
1
0
1
1
1
0
A0
Device Address
Instruction Byte The next byte sent to the X9421 contains the instruction and register pointer information. The four most significant bits are the instruction. The next two bits point to one of four Data Registers. The format is shown below in Figure 3. Figure 3. Instruction Byte Format
Register Select
I3
I2
I1
I0
R1
R0
0
0
Instructions
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The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits are defined as 0. Two of the eight instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: - XFR Data Register to Wiper Counter Register --This instruction transfers the contents of one specified Data Register to the Wiper Counter Register. - XFR Wiper Counter Register to Data Register--This instruction transfers the contents of the Wiper Counter Register to the specified associated Data Register. The basic sequence of the two byte instructions is illustrated in Figure 4. These two-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9421; either between the host and one of the Data Registers or directly between the host and the WCR. These instructions are: - Read Wiper Counter Register--read the current wiper position of the pot, - Write Wiper Counter Register--change current wiper position of the pot, - Read Data Register--read the contents of the selected data register; - Write Data Register--write a new value to the selected data register. - Read Status--This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The final command is Increment/Decrement. It is different from the other commands, because it's length is indeterminate. Once the command is issued, the master can clock the wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS SCK
SI 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0
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Figure 5. Three-Byte Instruction Sequence (Write)
CS SCL SI 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0 0 0 D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS SCL SI 0 S0 0 0 D5 D4 D3 D2 D1 D0 1 0 1 1 1 0 A0 I3 I2 I1 I0 R1 R0 0 0
Don't Care
Figure 7. Increment/Decrement Instruction Sequence
CS SCK
SI 0 1 0 1 1 1 0 A0 I3 I2 I1 I0 0 0 0 0 I N C 1 I N C 2 I N C n D E C 1 D E C n
Figure 8. Increment/Decrement Timing Limits
tWRID SCK
SI
VW INC/DEC CMD Issued
Voltage Out
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Table 3. Instruction Set Instruction
Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Read Status (WIP bit)
I3
1 1 1 1 1
I2
0 0 0 1 1
Instruction Set I1 I0 R1 R0
0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Operation
Read the contents of the Wiper Counter Register Write new value to the Wiper Counter Register Read the contents of the Data Register pointed to by R1-R0 Write new value to the Data Register pointed to by R1-R0 Transfer the contents of the Data Register pointed to by R1-R0 to the Wiper Counter Register Transfer the contents of the Wiper Counter Register to the Data Register pointed to by R1-R0 Enable Increment/decrement of the Wiper Counter Register Read the status of the internal write cycle, by checking the WIP bit.
1/0 1/0 1/0 1/0 1/0 1/0
1
1
1
0
1/0 1/0
0
0
0 0
0 1
1 0
0 1
0 0
0 0
0 0
0 1
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Instruction Format
Notes: (1) "A0": stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Wiper Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). (3) "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type device instruction wiper position identifier addresses opcode (sent by X9421 on SO) CS CS Falling Rising WWWWWW Edge 0 1 0 1 1 1 0 A 1 0 0 1 0 0 0 0 0 0 P P P P P P Edge 0 543210
Write Wiper Counter Register (WCR)
CS CS Falling W W W W W W Rising Edge 0 1 0 1 1 1 0 A 1 0 1 0 0 0 0 0 0 0 P P P P P P Edge 0 543210 device type identifier device addresses instruction opcode Data Byte (sent by Host on SI)
Read Data Register (DR) Read the contents of the Register pointed to by R1-R0.
device type device instruction register Data Byte identifier addresses opcode addresses (sent by X9421 on SO) CS CS Falling Rising WWWWWW Edge 0 1 0 1 1 1 0 A 1 0 1 1 R R 0 0 0 0 P P P P P P Edge 0 10 543210
Write Data Register (DR) Write a new value to the Register pointed to by R1-R0.
CS CS Falling W W W W W W Rising Edge 0 1 0 1 1 1 0 A 1 1 0 0 R R 0 0 0 0 P P P P P P Edge 0 10 543210 device type device identifier addresses instruction opcode register addresses Data Byte (sent by host on SI)
HIGH-VOLTAGE WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR) Transfer the contents of the Register pointed to by R1-R0 to the WCR.
device type device instruction register CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 1 1 0 A 1 1 0 1 R R 0 0 Edge 0 10
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Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type device instruction register CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 1 1 0 A 1 1 1 0 R R 0 0 Edge 0 10 HIGH-VOLTAGE WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type device instruction increment/decrement CS CS identifier addresses opcode (sent by master on SDA) Falling Rising Edge 0 1 0 1 1 1 0 A 0 0 1 0 0 0 0 0 I/D I/D . . . . I/D I/D Edge 0
Read Status
CS CS Falling W Rising Edge 0 1 0 1 1 1 0 A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge 0 P device type identifier device addresses instruction opcode Data Byte (sent by X9421 on SO)
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ABSOLUTE MAXIMUM RATINGS Temperature under bias . . . . . . . . . . . . -65C to +135C Storage temperature . . . . . . . . . . . . . . -65C to +150C Voltage on SCK any address input with respect to VSS . . . . . . . . . . . . . . . . . -1V to +7V V = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Lead temperature (soldering, 10 seconds) . . . . . . 300C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . 6mA Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . . VSS to VCC COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
Min.
0C -40C
Max.
+70C +85C
Device
X9421 X9421-2.7
Supply Voltage (VCC) Limits
5V 10% 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter
End to End Resistance Tolerance Power Rating Wiper Current Wiper Resistance
Min.
Limits Typ. Max.
20 50 3 250 1000 VCC -120 1.6 1 0.2 300 20 10/10/25 0.1
Units
% mW mA V dBV % MI(3) MI(3) ppm/C ppm/C pF A
Test Conditions
25C, each pot Wiper Current = 1mA, VCC = 5V Wiper Current = 1mA, VCC = 3V VSS = 0V Ref: 1kHz See Note 5 Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI] See Note 5 See Note 5 See Circuit #3 Vin = Vss to Vcc. Device is in stand-by mode.
IW RW
150 400
VTERM
Voltage on any VH/RH, VL/RL, VW/RW Noise Resolution(4) Absolute Linearity(1) Relative Linearity(2) Temperature Coefficient of RTOTAL Ratiometric Temperature Coefficient Potentiometer Capacitances Rh, RI, Rw leakage current
VSS
CH/CL/CW IAL
10
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH-VL)/63, single pot (4) Typical = Individual array resolution.
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL
Parameter
VCC Supply Current (Active) VCC Supply Current (Non-volatile Write) VCC Current (Standby) Input Leakage Current Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage
Min.
Typ.
Max.
400 1 1 10 10
Units
A mA A A A V V V
Test Conditions
fSCK = 2MHz, SO = Open, Other Inputs = VSS fSCK = 2MHz, SO = Open, Other Inputs = VSS SCK = SI = VSS, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC
VCC x 0.7 -0.5
VCC + 0.5 VCC x 0.1 0.4
IOL = 3mA
ENDURANCE AND DATA RETENTION Parameter
Minimum Endurance Data Retention
Min.
100,000 100
Units
Data Changes per Bit per Register Years
CAPACITANCE Symbol
COUT CIN
(5) (5)
Test
Output Capacitance (SO) Input Capacitance (A0, SI, and SCK)
Max.
8 6
Units
pF pF
Test Conditions
VOUT = 0V VIN = 0V
POWER-UP TIMING Symbol
tRVCC
(5)
Parameter
VCC Power up Ramp
Max.
0.2
Max.
50
Units
V/msec
POWER UP REQUIREMENTS (Power up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC and then the potentiometer pins, RH, RL, and RW. Voltage should not be applied to the potentiometer pins before VCC is applied. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC reaches its final value.
Notes: (5) This parameter is periodically sampled and not 100% tested.
A.C. TEST CONDITIONS Input pulse levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
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EQUIVALENT A.C. LOAD CIRCUIT
5V 1533 SDA Output 10pF 100pF 100pF RW 25pF 2.7V RH CH CW
Circuit #3 SPICE Macro Model
RTOTAL CL 10pF RL
AC TIMING Symbol
fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI Clock Frequency SSI/SPI Clock Cycle Time SSI/SPI Clock High Time SSI/SPI Clock Low Time Lead Time Lag Time SI, SCK, HOLD and CS Input Setup Time SI, SCK, HOLD and CS Input Hold Time SI, SCK, HOLD and CS Input Rise Time SI, SCK, HOLD and CS Input Fall Time SO Output Disable Time SO Output Valid Time SO Output Hold Time SO Output Rise Time SO Output Fall Time HOLD Time HOLD Setup Time HOLD Hold Time HOLD Low to Output in High Z HOLD High to Output in Low Z Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs CS Deselect Time WP, A0 and A1 Setup Time WP, A0 and A1 Hold Time 2 0 0 400 100 100 100 100 20 0 50 50 0 500 200 200 250 250 50 50 2 2 500 100
Parameter
Min.
Max.
2.0
Units
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns s ns ns
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HIGH-VOLTAGE WRITE CYCLE TIMING Symbol
tWR
Parameter
High-voltage Write Cycle Time (Store Instructions)
Typ.
5
Max.
10
Units
ms
XDCP TIMING Symbol
tWRPO tWRL tWRID
Parameter
Wiper Response Time After The Third (Last) Power Supply Is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction)
Min.
Max. Units
10 10 450 s s ns
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
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TIMING DIAGRAMS Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC tLAG
...
tWH
tFI LSB
tRI
...
SO
High Impedance
Output Timing
CS
SCK tV SO MSB tHO
...
tDIS
...
LSB
SI
ADDR
Hold Timing
CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH
...
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XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL MSB
SI
...
LSB
VW
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
VW
...
SI
ADDR
Inc/Dec
Inc/Dec
...
SO
High Impedance
Write Protect and Device Address Pins Timing
CS tWPASU WP A0 A1
(Any Instruction) tWPAH
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APPLICATIONS INFORMATION Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solidstate potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers
VR VH VW VL I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current VR
Basic Circuits
Buffered Reference Voltage R1 +V +5V VW VW X + - -5V OP-07 VOUT = VW +V R1 VW (a) (b) VO = (1+R2/R1)VS VW R2 Cascading Techniques +V +V VS + - -5V Noninverting Amplifier +5V LM308A VO
Voltage Regulator
Offset Voltage Adjustment
Comparator with Hysterisis
VIN
317 R1
VO (REG)
R1 VS 100K - +
R2
VS
- + VO
VO } } TL072 R1 R2
Iadj R2 10K 10K +12V 10K -12V
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VUL = {R1/CR1+R2} VO(max) VLL = {R1/CR1+R2} VO(min)
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X9421
PACKAGING INFORMATION 16-Lead Plastic SOIC (300 Mil Body) Package Type S
0.290 (7.37) 0.299 (7.60)
0.393 (10.00) 0.420 (10.65)
PIN 1 INDEX
PIN 1
0.014 (0.35) 0.020 (0.51) 0.403 (10.2 ) 0.413 ( 10.5)
(4X) 7
0.092 (2.35) 0.105 (2.65)
0.050 (1.27)
0.003 (0.10) 0.012 (0.30)
0.010 (0.25) 0.020 (0.50) X 45
0.050" Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.015 (0.40) 0.050 (1.27) 0.420" 0.050" Typical
FOOTPRINT
0.030" Typical 16 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 8/1/02
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Characteristics subject to change without notice.
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X9421
PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.6 8/1/02
www.xicor.com
Characteristics subject to change without notice.
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X9421
ORDERING INFORMATION
X9421 Device
Y
P
T
V VCC Limits Blank = 5V 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package S = 16-Lead SOIC V = 14-Lead TSSOP Potentiometer Organization W =10K Y =2.5K
LIMITED WARRANTY
(c)Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 1.1.6 8/1/02
www.xicor.com
Characteristics subject to change without notice.
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